This invention relates to a ferroelectric memory cell, and a method for its manufacture.
Electronic memory devices that include ferroelectric components integrated on a semiconductor can include a number of ferroelectric memory cells organized in a matrix form of rows and columns, coupled by word and bit lines, respectively.
Each ferroelectric memory cell has a MOS transistor and a ferroelectric capacitor.
Known processes for manufacturing such memory cells include, after the MOS transistor is integrated in a semiconductor substrate, covering the entire chip surface with an insulating layer.
The ferroelectric capacitor is formed on top of this insulating layer. The capacitor conventionally includes a lower electrode of metal placed onto the insulating layer. A ferroelectric material layer covers the lower electrode, and a metal upper electrode is laid onto the ferroelectric layer.
An electrode of the ferroelectric capacitor is then connected to a conduction electrode of the MOS transistor.
After forming the ferroelectric memory cell, the next metallization layers are formed as necessary to complete the memory circuit structure.
This solution has a number of drawbacks. The required treatment for the provision of metallization levels can damage the properties of the ferroelectric materials, and with it, the performance of a ferroelectric memory cell.
A prior approach to attenuating this problem is described by Amanuma in an article xe2x80x9cCapacitor-on-Metal/Via-stacked-Plug (CMVP) Memory Cell for 0.25 xcexcm CMOS Embedded FeRAMxe2x80x9d, published in March 1998 by IEEE and incorporated herein by this reference in toto.
The article describes a ferroelectric memory cell comprising a MOS transistor integrated in a semiconductor, the formation of two metallization levels followed by the formation of a ferroelectric capacitor, and ultimately the formation of a final metallization layer.
Although achieving its objective, not even this solution is devoid of drawbacks. The provision of a final metallization layer after forming the ferroelectric capacitor results, in fact, in degradation of the ferroelectric material.
Until now, no memory device or process for making a memory device was available to provide a ferroelectric memory cell with such construction and functional features as to retain the ferroelectric characteristics of its component materials and overcome the limitations and drawbacks that still beset prior art ferroelectric memory devices.
Embodiments of the invention provide a memory structure which has at least one ferroelectric memory cell consisting of a MOS transistor connected to a ferroelectric capacitor, wherein the ferroelectric capacitor is formed after all the metallization levels of the memory structure have been formed.
Presented is a memory cell integrated in a semiconductor substrate that has a MOS device with an overlying metallization layer. An insulating layer covers the metallization layer. Over the insulating layer is formed a capacitive element having a lower electrode covered with a layer of a dielectric material and capacitively coupled to an upper electrode. The metallization layer extends only between the MOS device and the lower electrode of the capacitive element. Also presented is a method to make the cell just described.
The invention relates, particularly but not exclusively, to a non-volatile ferroelectric memory cell, and the description to follow deals with this field of application for simplicity.